It would be awesome if anyone could help, thanks a lot! Now, normally I would use the 'length parameter in a function, but in this case I have a 2000 wide std_logic_vector but only need a part of it(n) for calculations Variable vPoly : std_logic_vector(n downto 0) := (others => '0') I got the same problem when declaring a function:įunction main (poly_in00:std_logic_vector n,k: natural) RETURN std_logic_vector is In this example I have to following problems: the signal lk gives the error: expression is not constant vhdl., does this mean that signals in vhdl HAVE to have constant widths? I would want to dynamically change the width of my std_logic_vector inputs or a least create signals that have dynamic width depending on an inputed natural, example: Hi, I'm finishing my final year project and while connecting a lot of components together I ran into a problem I missed while writing the first component.